1. Field of the Invention
The present invention relates generally to packaging substrates and methods for fabricating the same, and more particularly, to a packaging substrate with a reinforced electrical connection structure and a method for fabricating the same.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are becoming lighter, thinner, shorter and smaller. There is a trend towards high-performance, high-functionality, and high-speed electronic products. In a conventional semiconductor package structure, an inactive surface of a semiconductor chip is attached to a packaging substrate and an active surface of the semiconductor chip is electrically connected to the packaging substrate through bonding wires. Alternatively, the active surface of the semiconductor chip can be electrically connected to the packaging substrate by flip-chip technique. Further, a plurality of solder balls are mounted on the back side of the packaging substrate so as to electrically connect the semiconductor chip to a printed circuit board.
FIG. 1 is a sectional view of a conventional packaging substrate, wherein both wire bonding and flip-chip techniques are used for electrically connecting semiconductor chips to the packaging substrate. As shown in FIG. 1, first, a substrate body 10 having a first surface 10a and an opposing second surface 10b is provided, wherein on the first surface 10a are a plurality of flip-chip solder pads 101 and wire bonding pads 102, and the second surface 10b has a plurality of solder ball pads 103 thereon. A first solder mask layer 11a and a second solder mask layer 11b are formed on the first and second surfaces 10a, 10b, respectively. A plurality of first openings 110a, second openings 111a and third openings 110b are formed in the first and second solder mask layers 11a, 11b for exposing the flip-chip solder pads 101, the wire bonding pads 102 and the solder ball pads 103, respectively. A surface treatment layer 12 is formed on the wire bonding pads 102 and the solder ball pads 103. Solder bumps 13 are formed on the flip-chip solder pads 101. The surface treatment layer 12 is an electroplated or electroless Ni/Au layer, and the solder bumps are made of SnPb, SnAg, SnCu, or SnAgCu. Alternatively, only a surface treatment layer (not shown) made of organic solderability preservative (OSP) coatings, immersion tin (IT) or a solder material is formed on the flip-chip solder pads 101.
A first semiconductor chip 14a is mounted on the flip-chip solder pads 101 through the solder bumps 13. The first semiconductor chip 14a has an active surface 141a and an inactive surface 142a. A plurality of first electrode pads 143a are disposed on the active surface 141a and connected to the solder bumps 13 through a plurality of conductive bumps 144 such that the first semiconductor chip 14a is flip-chip electrically connected to the substrate body 10.
Further, a second semiconductor chip 14b is mounted on the first semiconductor chip 14a when the inactive surface 142b of the second semiconductor chip 14b is coupled to the inactive surface 142a of the first semiconductor chip 14a by a bonding material 15 provided therebetween. A plurality of second electrode pads 143b are disposed on an active surface 141b of the second semiconductor chip 14b and electrically connected to the wire bonding pads 102 by conductive wires 16 made of gold (Au). Further, a molding material 17 is formed to cover the first solder mask layer 11a, the wire bonding pads 102, the conductive wires 16, and the first and second semiconductor chips 14a, 14b for protection.
However, owing to the trend towards increasingly compact electronic devices, the pitches between the flip-chip solder pads 101, the wire bonding pads 102 and the solder ball pads 103 are continuously decreasing. Also, the diameter of the first and third openings 110a, 110b decreases relatively, and the exposed area of the flip-chip solder pads 101 and the solder ball pads 103 also decreases, thereby resulting in reduced bonding area between the flip-chip solder pads 101 and the solder bumps 13 as well as the solder ball pads 103 and solder balls (not shown). Further, with the flip-chip solder pads 101, the wire bonding pads 102 and the solder ball pads 103 being generally made of copper, the surface treatment layer 12 and the solder bumps 13 have to meet a lead-free soldering requirements, the surface treatment layer 12 and the solder bumps 13 face the following problems that may adversely affect the electrical connection reliability.
Firstly, with the surface treatment layer 12 being made of a solder material (SnPb, SnAg, SnCu, SnAgCu), immersion tin or OSP, it is difficult to prevent copper migration that may otherwise cause a short circuit. Further, along with the continuous increase of the thickness of an IMC (intermetallic compound) layer formed at the Sn—Cu interface, the thickness of the flip-chip solder pads 101 and the solder ball pads 103 continuously decreases, thereby adversely affecting the joint reliability.
Secondly, the surface treatment layer 12 which is an electroplated Ni/Au layer does not have fine-pitch applications for failure to meet evenness requirements for the fine-pitch applications. With the surface treatment layer 12 being formed on the flip-chip solder pads 101 or solder ball pads 103, the solder bumps 13 or solder balls readily come off the surface treatment layer 12. With the surface treatment layer 12 being formed on the wire bonding pads 102, the conductive wires 16 readily come off the surface treatment layer 12.
Thirdly, with the surface treatment layer 12 made of electroless Ni/Au being formed on the flip-chip solder pads 101 or the solder ball pads 103, the solder bumps 13 or solder balls readily come off the surface treatment layer because of the characteristics of Ni. Therefore, the surface treatment layer cannot be applied to hand-held products. If the surface treatment layer is formed on the wire bonding pads 102, there will be poor attachment between the Au layer and the conductive wires 16 because the Au layer formed by electroless plating is quite thin and structurally weak.
Fourthly, if the solder bumps 13 are formed by screen printing, a fine pitch cannot be achieved because the average size and height tolerance of the solder bumps 13 cannot be controlled well enough. If the solder bumps 13 are formed on the flip-chip solder pads 101 and the average size or height of the solder bumps 13 is small, an underfill process can be adversely affected. On the other hand, large average size or height of the solder bumps 13 is conducive to providing a solder bridge which is likely to cause a short circuit. In addition, given large height tolerance of the solder bumps 13, chips can easily be damaged due to uneven joint stresses caused by poor coplanarity.
Therefore, the semiconductor industry is in dire need of a solution to overcome the above drawbacks.